The present invention relates to a semiconductor device and a fabrication method therefor, and, in particular, to a semiconductor device having an interlayer dielectric and a fabrication therefor that enables fabrication at below the half-micron level.
In a semiconductor device such as an LSI, recent advances in miniaturization, integration, and multi-layering of electronic elements have raised vital technical problems concerning lowering the temperature at which interlayer dielectrics are formed, flattening those layers, and the techniques used for forming metal wiring.
To form such an interlayer dielectric, a silicon oxide layer is first grown at a low temperature by chemical vapor deposition on a substrate on which an electronic element or the like has been formed, then a vapor-phase reaction is induced between a silane compound, oxygen, or ozone and a gas containing an impurity such as phosphorus or boron to form a layer of a boron-phospho silicate glass (BPSG) to a thickness of several hundred nm to 1 .mu.m. Subsequently, the layer is annealed at a high temperature in a nitrogen environment, to cause the BPSG film to liquefy in a high-temperature flow, to flatten it. After through-holes (contact holes) are formed in the thus-fabricated interlayer dielectric and a barrier layer of titanium or titanium nitride is formed thereon, a metal wiring layer is formed.
This flattening of the interlayer dielectric that uses a BPSG film makes use of the high-temperature flow characteristics of the BPSG film, and the flattening proceeds faster as the density of impurities in the BPSG film and the temperature of the annealing increase. To obtain a sufficient degree of flatness and fineness of the BPSG film, an annealing temperature of at least 850.degree. C. is required.
However, to prevent the occurrence of punch-through between miniaturized MOS transistors, it is important to suppress any excessive broadening of the source and drain impurity layers caused by the annealing, and thus it is preferable to keep the processing temperature to not more than 850.degree. C. When a layer of a silicide such as titanium silicide is formed on the surfaces of the source and drain impurity layers that configure a MOS transistor, high-temperature annealing will cause the region of the silicide layer to become broader than necessary, which leads to deterioration of the connectivity characteristics. For that reason, there is a demand for a technique that makes it possible to form this interlayer dielectric at a relatively low temperature.